ALPHA15 User Guide

Getting started

Warnings

The ALPHA15 power supply must be turned off before connecting or disconnecting:

• the micro-SD card
• peripherals on the expansion connector

Power up the board

First, insert the micro-SD card into the micro-SD slot. Then connect the 12V jack of the power supply. The power good green LED (PWGD) and the FPGA done orange LED (DONE) indicate the system has correctly started.

Communicating with the board

LAN

The ethernet port is the main communication interface with the ALPHA15. It can be connected to a local network via a router or directly to a computer. The last 8 bits of the IP address are displayed on the 8 user LEDs.

Serial interface

The serial UART debugging interface can be accessed by the micro USB connector. The required steps are described here.

Connectors

12 V external power supply

The external supply connector is a jack with 1.95 mm center pin and 6 mm outer diameter. Only 12 V must be supplied on this connector. Running the ALPHA15 requires at least 1 A. More current may be required depending on the load on the expansion connector. Maximum current is 3 A (protected by an electronic fuse).

USB 2.0

This is a USB 2.0 host connector. It provides up to 1 A current at 5 V (shared with the 5 V supply of the expansion connector). The power and data pins are ESD protected.

Micro USB 2.0

Connects to the UART0 PS core via a FTDI device. It is used as a debugging serial interface. The power and data pins are ESD protected.

Gigabit ethernet

The ALPHA15 is capable of 10/100/1000 Mbit Ethernet.

MicroSD card

The micro SD card is connected to the SD0 PS core via a level-shifter. The SD card I/Os are ESD protected.

Expansion connector

It contains:

• Power supplies. 12 V from external supply. 5 V up to 1 A (shared with USB 2.0 connector). +3.3 V up to 800 mA, sequenced with bank 35 I/Os supply. -3.3 V up to 500 mA. +2.5 V up to 50 mA, sequenced with bank 34 I/Os supply

• A dedicated I2C bus I2C1 with interrupt.

• 10 single ended or 5 differential I/Os EXP_IOAx. They are connected to the FPGA Bank 34. Voltage level is 2.5 V. All I/Os are ESD protected. Warning: These pins are connected directly to the Zynq SoC and must be driven from VCCIO_2V5, both for voltage compliance and power sequencing. Applying non compliant voltages on these pins may result in SoC failure.

• 16 single ended I/Os EXP_IOBx. They are connected to the FPGA Bank 35. Voltage level is 3.3 V. All I/Os are ESD protected. Warning: These pins are connected directly to the Zynq SoC and must be driven from VCCIO_3V3, both for voltage compliance and power sequencing. Applying non compliant voltages on these pins may result in SoC failure.

• One LVDS clock from the clocking subsystem EXP_CLK.

• Two voltage references 4.096 V and 2.5 V. This references have ratiometric tracking between them and with the data converters references.

• 4 precision DAC outputs. Outputs from the 16-bit precision DAC.

Subsystems

ADC (18-bit, 15 Msps)

The ALPHA15 contains two high-speed (15 Msps), high-resolution (18-bit) ADCs (Analog Devices LTC2387-18).

ADC inputs are labeled IN0 and IN1 on the SMA connectors. The inputs are DC coupled and 1 MΩ terminated. The inputs are protected by a transient voltage suppressor limiting the absolute maximum input voltage to ±8 V. The input range can be selected with the RF_ADCx_RANGE_SEL signal (0 = 2 Vpp / 1 = 8 Vpp).

The ALPHA15 encoding clocks of the ADC0 and ADC1 are provided by the clocking system outputs RF_ADC0_CNV and RF_ADC1_CNV respectively.

The ADC is interfaced to the I/O Bank 34 of the FPGA (2.5 V logic). The transfer protocol is described in the LTC2387-18).

RF DAC

The RF Digital-to-Analog Converter has 2 outputs with 16-bit resolution and 250 Msps maximum sampling rate (Analog Devices AD9747). The outputs are labeled OUT0 and OUT1 on the SMA connectors. Output impedance is 50 Ω. The outputs are protected by a transient voltage suppressor clamping over-voltages beyond ±8 V.

The output range is 1.5 V_pp maximum in a 50 Ω load. It can be adjusted using the DAC gain on the configuration SPI bus. In the default configuration, the DAC outputs 1 V_pp in a 50 Ω load.

The sampling clock of the DAC is provided by the RF_DAC_CLK of the clocking system. The input data lines are interfaced to the I/O Bank 35 of the FPGA. It consists of 32 single-ended lines at 3.3 V.

The RF DAC is configured by the configuration SPI bus. The source code of the corresponding C++ driver is on Github.

Clocking

The clocking system is organized around the ultra-low phase noise clock generator (Texas Instruments LMK04906). A dual PLL setup is used. The first loop locks an ultra-low phase noise VCXO (ABLNO-V-100.000MHz) onto a reference clock. It serves as a phase-noise cleaner for the reference clock. The second loop locks the LMK04906 internal VCO (2.37 to 2.6 GHz) onto the VCXO. A set of clock dividers allows to produce up to six clocks at desired frequencies.

The clock generator is designed to accept 10 MHz reference clocks.

The reference clock sources are:

• The CLKI SMA input on the board. It is a 50 Ω impedance input that accepts an AC voltage of up to 2.5 V_pp (10 dBm). It also supports up to 5 V_DC. An onboard precision high-speed comparator (890 Mbps) provides effective clock recovery. It is ESD protected.

• The FPGA_CLK_OUT signal to discipline the system on a clock provided by the FPGA.

• The onboard 10 MHz temperature compensated voltage controlled crystal oscillator (TCVCXO). It has a tight stability (±280 ppb over the industrial temperature range -40 to +85 °C). Its aging is ±1 ppm per year maximum. A DAC controlled from the I2C0 bus can be used to precisely tune its frequency.

The clock generator produces the following clocks:

• An LVCMOS clock available on the board CLKO SMA output. This output is ESD protected.
• RF ADC sampling clock(s) RF_ADCx_CNV distributed as an LVDS signal.
• RF DAC sampling clock RF_DAC_CLK distributed as an LVDS signal.
• FPGA_CLK_IN is an LVDS input clock on the FPGA.
• EXP_CLK is a LVDS clock available on the expansion connector.

The clock generator is configured by the configuration SPI bus via the ClockGenerator driver.

Precision DAC

The precision DAC is a 4-channel, 16-bit DAC (Analog Devices AD5686).

The output voltage ranges from 0 to 2.5 V. It includes an output buffer that can deliver up to 20 mA per channel. The outputs are ESD protected.

The four output channels are available on the expansion connector. Communication with the precision DAC is done through a dedicated SPI bus via the PrecisionDac driver.

Temperature sensors

The ALPHA15 has two high-accuracy temperature sensors (TMP116) with an accuracy of ±0.2 °C over -10 °C to +85 °C. One sensor is placed near the voltage reference (T0 highlighted in blue) to allow temperature compensation in high precision measurements. The other one is placed between the clock generator and the RF ADC which is close to the hottest point on the board (T1 highlighted in red).

The Zynq temperature T2 is also monitored using the XADC on the FPGA. The TemperatureSensor driver allows to retrieve the 3 above temperatures. For reliable operation, make sure that T1 < 70 °C and T2 < 85 °C.

Power monitors

The ALPHA15 includes two power monitors (Texas Instruments INA230). Two rails are monitored: the external 12 V power supply and the clocking subsystem supply. In both cases, the current shunt resistor is 10 mΩ. Both power monitors are accessible on the I2C0 bus via the PowerMonitor driver.

EEPROM

The ALPHA250 has a 64-kbit EEPROM (Microchip 24AA64T-I/MC). It is accessible on the I2C0 bus via the Eeprom driver.

The EEPROM is divided into two parts. The lower addresses are used by Koheron to store identification and calibration data. The higher addresses (above 0x1000) are for user applications. The EEPROM map addressing is given in the table below.

Zynq I/Os

The Zynq XC7Z020-2CLG400I has 2 I/O banks for the programmable logic (Banks 34 and 35) with 48 IOs each. One bank (Bank 0) is dedicated to the processing system with a multiplexed I/O (MIO) interface. The set of peripherals and interface buses is depicted below.

I/O constraints are defined in the ports.xdc file.

ADC data bus

The RF ADC is interfaced to the Bank 34 by a LVDS data bus. By default the LTC2367 core operates in two-lane output mode, and data are transfered on the two lines DA (for odd bits) and DB (for even bits).

# RF ADC0 (Bank 34)

# Clock output
set_property IOSTANDARD LVDS_25 [get_ports adc0_clk*]

set_property PACKAGE_PIN P20 [get_ports adc0_clk_out_n]
set_property PACKAGE_PIN N20 [get_ports adc0_clk_out_p]

# Data inputs
set_property IOSTANDARD LVDS_25 [get_ports adc0_d*]
set_property DIFF_TERM TRUE [get_ports adc0_d*]

set_property PACKAGE_PIN P18 [get_ports adc0_db_n]
set_property PACKAGE_PIN N17 [get_ports adc0_db_p]
set_property PACKAGE_PIN W20 [get_ports adc0_da_n]
set_property PACKAGE_PIN V20 [get_ports adc0_da_p]
set_property PACKAGE_PIN U20 [get_ports adc0_dco_n]
set_property PACKAGE_PIN T20 [get_ports adc0_dco_p]

# Control pins
set_property IOSTANDARD LVCMOS25 [get_ports adc0_ctl*]

set_property PACKAGE_PIN V15 [get_ports adc0_ctl_range_sel]
set_property PACKAGE_PIN Y19 [get_ports adc0_ctl_twolanes]
set_property PACKAGE_PIN W18 [get_ports adc0_ctl_testpat]
set_property PACKAGE_PIN W19 [get_ports adc0_ctl_en]

# RF ADC1 (Bank 34)

# Clock output
set_property IOSTANDARD LVDS_25 [get_ports adc1_clk*]

set_property PACKAGE_PIN P19 [get_ports adc1_clk_out_n]
set_property PACKAGE_PIN N18 [get_ports adc1_clk_out_p]

# Data inputs
set_property IOSTANDARD LVDS_25 [get_ports adc1_d*]
set_property DIFF_TERM TRUE [get_ports adc1_d*]

set_property PACKAGE_PIN T15 [get_ports adc1_db_n]
set_property PACKAGE_PIN T14 [get_ports adc1_db_p]
set_property PACKAGE_PIN U17 [get_ports adc1_da_n]
set_property PACKAGE_PIN T16 [get_ports adc1_da_p]
set_property PACKAGE_PIN P16 [get_ports adc1_dco_n]
set_property PACKAGE_PIN P15 [get_ports adc1_dco_p]

# Control pins
set_property IOSTANDARD LVCMOS25 [get_ports adc1_ctl*]

set_property PACKAGE_PIN W15 [get_ports adc1_ctl_range_sel]
set_property PACKAGE_PIN Y17 [get_ports adc1_ctl_testpat]
set_property PACKAGE_PIN Y18 [get_ports adc1_ctl_en]

RF DAC parallel bus

The RF DAC is interfaced to the Bank 35 by a LVCMOS 3V3 parallel bus. The data for each channel are transferred on a 16 line sub-bus. The configuration is performed via the configuration SPI bus.

# RF DAC

set_property IOSTANDARD LVCMOS33 [get_ports dac_*]
set_property DRIVE 8 [get_ports dac_*]

# Channel 0
set_property PACKAGE_PIN D18 [get_ports {dac_0[0]}]
set_property PACKAGE_PIN E17 [get_ports {dac_0[1]}]
set_property PACKAGE_PIN E19 [get_ports {dac_0[2]}]
set_property PACKAGE_PIN E18 [get_ports {dac_0[3]}]
set_property PACKAGE_PIN A20 [get_ports {dac_0[4]}]
set_property PACKAGE_PIN B19 [get_ports {dac_0[5]}]
set_property PACKAGE_PIN F17 [get_ports {dac_0[6]}]
set_property PACKAGE_PIN F16 [get_ports {dac_0[7]}]
set_property PACKAGE_PIN B20 [get_ports {dac_0[8]}]
set_property PACKAGE_PIN C20 [get_ports {dac_0[9]}]
set_property PACKAGE_PIN L17 [get_ports {dac_0[10]}]
set_property PACKAGE_PIN L16 [get_ports {dac_0[11]}]
set_property PACKAGE_PIN D20 [get_ports {dac_0[12]}]
set_property PACKAGE_PIN D19 [get_ports {dac_0[13]}]
set_property PACKAGE_PIN G18 [get_ports {dac_0[14]}]
set_property PACKAGE_PIN G17 [get_ports {dac_0[15]}]

# Channel 1
set_property PACKAGE_PIN F20 [get_ports {dac_1[0]}]
set_property PACKAGE_PIN F19 [get_ports {dac_1[1]}]
set_property PACKAGE_PIN J16 [get_ports {dac_1[2]}]
set_property PACKAGE_PIN K16 [get_ports {dac_1[3]}]
set_property PACKAGE_PIN G20 [get_ports {dac_1[4]}]
set_property PACKAGE_PIN G19 [get_ports {dac_1[5]}]
set_property PACKAGE_PIN K18 [get_ports {dac_1[6]}]
set_property PACKAGE_PIN K17 [get_ports {dac_1[7]}]
set_property PACKAGE_PIN H20 [get_ports {dac_1[8]}]
set_property PACKAGE_PIN J20 [get_ports {dac_1[9]}]
set_property PACKAGE_PIN M18 [get_ports {dac_1[10]}]
set_property PACKAGE_PIN M17 [get_ports {dac_1[11]}]
set_property PACKAGE_PIN H18 [get_ports {dac_1[12]}]
set_property PACKAGE_PIN J18 [get_ports {dac_1[13]}]
set_property PACKAGE_PIN G15 [get_ports {dac_1[14]}]
set_property PACKAGE_PIN H15 [get_ports {dac_1[15]}]

Configuration SPI bus

A shared SPI bus is dedicated to the configuration of the RF ADC, the RF DAC and the clock generator. In the reference design, a HDL core is used for the communication on this bus. The interface is described below.

Constraint file

The configuration SPI bus pins are connected to Bank 34 with 2.5 V LVCMOS signals.

# Configuration SPI (Bank 34)
set_property IOSTANDARD LVCMOS25 [get_ports spi_cfg_*]

set_property PACKAGE_PIN R17 [get_ports spi_cfg_sdo]
set_property PACKAGE_PIN R16 [get_ports spi_cfg_sdi]
set_property PACKAGE_PIN W16 [get_ports spi_cfg_sck]

set_property PACKAGE_PIN U12 [get_ports spi_cfg_cs_rf_dac]
set_property PACKAGE_PIN T12 [get_ports spi_cfg_cs_clk_gen]

Transfer core

The core is write only. It does not read back configurations from the chips. The s_axis_tready signal can be used to determine when the core finishes sending a message and is ready to send a new one.

The core can send 1, 2, 3 or 4 bytes of data. The number of bytes to transfer is specified using the bits B2 and B3 of the cmd byte according to the table below.

Configuration SPI byte transfer count

The chip select address is specified using the bits B0 and B1 of the cmd byte according to the table below.

Configuration SPI chip select address

The transferred data must be wired to the s_axis_tdata pin. The transfer is triggered on the s_axis_tvalid pin falling edge. The core is controlled via the SpiConfig driver.

Precision DAC SPI bus

Data is transferred to the precision DAC using a SPI bus that can be clocked up to 50 MHz. In addition, a latched pin LDAC pin is used to update the 4 channel outputs synchronously. In the reference design, a dedicated HDL core is used. The interface is shown below.

Constraint file

The precision DAC SPI pins are connected to the Bank 34 with 1.8 V LVCMOS signals.

# Precision DAC (Bank 34)
set_property IOSTANDARD LVCMOS25 [get_ports spi_precision_dac_*]

set_property PACKAGE_PIN V17 [get_ports spi_precision_dac_cs]
set_property PACKAGE_PIN V18 [get_ports spi_precision_dac_sck]
set_property PACKAGE_PIN T17 [get_ports spi_precision_dac_sdi]
set_property PACKAGE_PIN R18 [get_ports spi_precision_dac_ldac]

Transfer core

While the valid is high, the core updates the DAC channels with the values on pin data. The 64 bits of the data pin contain the concatenation of the 4 x 16 bits values to be set on the 4 channels. Channel 0 being on the 16 least significant bits, followed by channels 1, 2 and 3. After sending the data for the 4 channels, the core latches ldac. The data will be synchronously updated if cmd = 1. If cmd = 3, the output is updated as new values arrive. The core is written in Verilog. It is controlled with the PrecisionDac driver.

PS cores

The processing system contains hard cores (by opposition with the soft cores that can be deployed on the PL). The PS cores are interfaced with MIO pins on Bank 0. The logic level is LVCMOS 1.8 V. MIO configuration can be found in the board configuration file.

The constraints file for the PS is:

set_property CFGBVS GND [current_design]
set_property CONFIG_VOLTAGE 1.8 [current_design]

I2C0

This bus is used on the ALPHA250 internally and is not accessible from the expansion connector. The I2C0 bus addressing is:

• 1100100 / 1011100: Secure EEPROM
• 1010001: RTC registers
• 1010100: User EEPROM
• 0100000: GPIO expander
• 1000001: Main power supply monitor
• 1000101: Clocking subsystem supply monitor
• 1001000: Voltage reference temperature sensor
• 1001001: Board temperature sensor
• 0101111: TCXO control voltage

I2C1

The I2C1 bus is for the expansion connector. A 3.3 V level shifter with 2.2 kΩ pull-ups provides the interface with the Bank 0. The I2C1 core can be replaced with a CAN core CAN0 with proper PS configuration.

ENET0

The ethernet peripheral is interfaced with the ENET0 MAC core.

USB0

The USB 2 connector is interfaced with the USB0 core.

SD0

The SD card is interfaced with the SD0 core.

UART0

The serial port debugging USB interface connects to the UART0 core.