FPGA design
Overview
The FPGA design of an instrument relies on:
- Xilinx Zynq board and Xilinx Design Constraints (XDC) files
- FPGA cores
- FPGA modules (optional)
- Vivado block design
Boards
Available boards by default are:
- Red Pitaya
- Zedboard
The board directory must be specified in the instrument configuration file.
Koheron SDK provides default boards XDC files.
XDC files must be specified in the instrument configuration file.
FPGA cores
Koheron SDK provides a library of FPGA cores.
A core can be tested with the following command:
$ make CORE=fpga/modules/axi_ctl_register_v1_0 test_core
Cores must be specified in the instrument configuration file.
FPGA modules
FPGA modules include their own Vivado block design with a test bench file testbench.v written in Verilog.
Koheron SDK provides a library of FPGA modules.
A module can be tested with the following command:
$ make CONFIG=fpga/modules/address/config.yml test_module
Modules must be specified in the instrument configuration file.
Block design
Koheron SDK uses a block design Tcl script to create the instrument block design.
